Computer Systems Group Design Issues for Latency Hiding on an Access Decoupled

Future software and hardware technologies will try to provide improved performance by extracting higher levels of parallelism. However the cost of a main memory access-in terms of missed instruction slots-increases with faster processors and greater issue widths. For this reason latency hiding technology remains one of the most important parts of high performance processor designs. In this paper we investigate a latency hiding technique known as Access Decoupling which partitions a program into two separate instruction streams in order to aggressively prefetch data. We justify a renewed interest in Access Decoupling in two ways. Firstly as a latency hiding technique and secondly as a solution to the problem of hardware complexity in large issue width, out-of-order superscalar architectures. We show that in comparison to a single instruction stream architecture Access Decoupling is marginally more eeec-tive at hiding memory latency and capable of achieving higher performance through its simpler design. After providing our justiication for renewed interest in the decoupling paradigm we quantify the performance impact of diierent hardware/software design issues on Access Decoupled machines. We consider the eeect of restrictions imposed by data dependency analysis, renaming, memory reordering, operation reordering, issue width and 1 synchronisation points on IPC and latency hiding eeectiveness.